{"id":13,"date":"2015-09-30T12:06:51","date_gmt":"2015-09-30T11:06:51","guid":{"rendered":"https:\/\/blogs.ncl.ac.uk\/jrbeaumont\/?p=13"},"modified":"2015-10-22T10:14:24","modified_gmt":"2015-10-22T09:14:24","slug":"designing-asynchronous-logic-gates-using-behavioural-concepts-i-a-buffer-2","status":"publish","type":"post","link":"https:\/\/blogs.ncl.ac.uk\/jrbeaumont\/2015\/09\/30\/designing-asynchronous-logic-gates-using-behavioural-concepts-i-a-buffer-2\/","title":{"rendered":"Concepts I: A buffer"},"content":{"rendered":"

A Buffer<\/span><\/strong><\/p>\n

In this post, we will discuss\u00a0one of the most simple logic gates, a buffer<\/em>.<\/p>\n

\"buffer_schematic\"<\/a><\/p>\n

A buffer takes an input signal, and outputs a signal in the same state as the input signal, the output simply follows the input. For example, if the input signal changes from 0 to 1, the output will eventually change from 0 to 1. We say the output changes \u2018eventually\u2019 because the output changes after some unknown delay. It is possible for the input to change from 0 to 1, and then back to 0 very quickly, before we see any changes on the output. But intuitively, we want to be able to say that if the input transitions from 0 to 1, then stays 1 long enough, the output will follow and also transition to 1.<\/p>\n

So how can we design\u00a0these using concepts? We need to describe the causal relationship between the input and output; what occurs in the input to cause a transition in\u00a0the output? For a buffer, this is when a signal transition occurs on the input, this needs to be reflected on the output.\u00a0 This\u00a0can be described as:<\/p>\n

buffer(in, out) = in+ <\/strong>\u21dd out+ <\/strong>\u22c4 in- <\/strong>\u21dd out-<\/strong><\/p>\n

There are some operators to discuss here:<\/p>\n

\u21dd – Shows the causal relationship
\n\u22c4\u00a0\u00a0– The composition operator<\/p>\n

This concept therefore implies that in+<\/strong> causes out+<\/strong>, this is composed with in-<\/strong> causing out-<\/strong>.\u00a0 This covers all the operations of the buffer.<\/p>\n

But now, how does this turn into a Signal Transition Graph, which we can simulate, verify and test to ensure it works correctly? This is performed using an algorithm:<\/p>\n

\"Buffer0\"<\/a><\/p>\n

First of all, the algorithm takes the list of concepts and finds places one of these cycle\u00a0for each individual signal. This is to keep with the property of consistency<\/em>, where positive (+<\/strong>) and negative (–<\/strong>) transitions of each signal must always alternate. This is also in-keeping with the possibility for a signal to transition one way and back quickly without affecting the others, as with the example of the input transitioning high and then low before the output changes.<\/p>\n

\"buffer1\"<\/a><\/p>\n

Next, the algorithm uses the first concept, in+ <\/strong>\u21dd<\/strong> out+<\/strong>, to show this causality in the STG. This concept shows how the input rising causes the output to rise, so this is viewed in an STG by connecting the in_1<\/strong> place, which shows when the input has transitioned high, to the transition of out+<\/strong>. This is done using an arc\u00a0commonly known as a read-arc. This is because a one way arc connecting these STG components would mean that when out+<\/strong> occurs, a token in in_1<\/strong> is consumed, blocking in-<\/strong> from being enabled. A read-arc allows out+<\/strong> to simply check for a token in in_1<\/strong> for it to occur without consuming it.<\/p>\n

\"Buffer2\"<\/a><\/p>\n

In the final step for designing a buffer, another read arc is used which represents the concept of in- <\/strong>\u21dd<\/strong> out<\/strong>-, connecting in_0<\/strong> place with the out-<\/strong> transition. This conversion of a concept to an STG is now complete.<\/p>\n

Note that in the above STGs we assume that all signals are initialised to 0.\u00a0 In a later blog post we will see how to use concepts to specify initial states of all signals in a compositional manner.<\/p>\n

Reuse<\/span><\/strong><\/p>\n

Now we have defined a buffer, we can reuse this. As said earlier in this post, a concept can be defined as several concepts. Therefore, let use an example of a circuit which uses buffers.<\/p>\n

\"double_buffer_schematic\"<\/a><\/p>\n

This circuit can be produced from the following concept:<\/p>\n

doubleBuffer = buffer(a,b) <\/strong>\u22c4<\/strong> buffer(b,c)<\/strong><\/p>\n

In this circuit, a<\/strong> is an input, c<\/strong> is an output, and b<\/strong> is an internal signal connecting the output of buffer_1<\/strong> to the input of buffer_2<\/strong>. We could have described this using signal-level concepts, which would be a longer description that that of the one above. Since we have defined a buffer, we can simply reuse this definition in order to save time on describing concepts. This produces the following Signal Transition Graph:<\/p>\n

\"doubleBufferSTG\"<\/a><\/p>\n

Comparing this STG to the STG for a single buffer, it is possible to see that a<\/strong> and b<\/strong> in this STG\u00a0form one buffer, and b <\/strong>and c<\/strong> form another buffer.\u00a0 Again, we assume that all signals are initially 0.<\/p>\n

Finally<\/strong><\/span><\/p>\n

In this first blog post, we have discussed how to describe a simple logic gate, a buffer, in terms of concepts. How these concepts are then converted into a Signal Transition Graph is also described. Another useful aspect of concepts is their reusability, and how a defined concept can be reused is displayed in an example using two buffers.<\/p>\n

The following post, Concepts II: An inverter <\/em><\/strong>will discuss another simple logic gate, an inverter. After having defined these two gates, a further post will explain how initial states work, whether defined as part of a concept or not, using both a buffer and an inverter as examples.<\/p>\n","protected":false},"excerpt":{"rendered":"

A Buffer In this post, we will discuss\u00a0one of the most simple logic gates, a buffer. A buffer takes an input signal, and outputs a signal in the same state as the input signal, the output simply follows the input. For example, if the input signal changes from 0 to 1, the output will eventually … Continue reading Concepts I: A buffer<\/span> →<\/span><\/a><\/p>\n","protected":false},"author":6010,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[3,5,2,6],"tags":[],"class_list":["post-13","post","type-post","status-publish","format-standard","hentry","category-asynchronous","category-buffer","category-concepts","category-logic-gate"],"_links":{"self":[{"href":"https:\/\/blogs.ncl.ac.uk\/jrbeaumont\/wp-json\/wp\/v2\/posts\/13","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.ncl.ac.uk\/jrbeaumont\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.ncl.ac.uk\/jrbeaumont\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.ncl.ac.uk\/jrbeaumont\/wp-json\/wp\/v2\/users\/6010"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.ncl.ac.uk\/jrbeaumont\/wp-json\/wp\/v2\/comments?post=13"}],"version-history":[{"count":15,"href":"https:\/\/blogs.ncl.ac.uk\/jrbeaumont\/wp-json\/wp\/v2\/posts\/13\/revisions"}],"predecessor-version":[{"id":77,"href":"https:\/\/blogs.ncl.ac.uk\/jrbeaumont\/wp-json\/wp\/v2\/posts\/13\/revisions\/77"}],"wp:attachment":[{"href":"https:\/\/blogs.ncl.ac.uk\/jrbeaumont\/wp-json\/wp\/v2\/media?parent=13"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.ncl.ac.uk\/jrbeaumont\/wp-json\/wp\/v2\/categories?post=13"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.ncl.ac.uk\/jrbeaumont\/wp-json\/wp\/v2\/tags?post=13"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}