{"id":58,"date":"2015-10-21T14:12:27","date_gmt":"2015-10-21T13:12:27","guid":{"rendered":"https:\/\/blogs.ncl.ac.uk\/jrbeaumont\/?p=58"},"modified":"2015-11-23T14:00:05","modified_gmt":"2015-11-23T14:00:05","slug":"concepts-ii-an-inverter","status":"publish","type":"post","link":"https:\/\/blogs.ncl.ac.uk\/jrbeaumont\/2015\/10\/21\/concepts-ii-an-inverter\/","title":{"rendered":"Concepts II: An inverter"},"content":{"rendered":"

An inverter<\/span><\/strong><\/p>\n

In the second post in the Concepts<\/em> series we will discuss another simple logic gate, an inverter<\/em>.<\/p>\n

\"inverter\"<\/a><\/p>\n

An inverter takes an input signal, and outputs a signal in the\u00a0opposite, or inverted,\u00a0state as the input signal, the output is simply the opposite of the input. For example, if the input signal changes from 0 to 1, the output will eventually change from\u00a01 to 0. Similar to with the buffer, and the same with all gates, we say the output changes \u2018eventually\u2019 because the output changes after some unknown delay.<\/p>\n

So how\u00a0do we design\u00a0an inverter\u00a0using concepts? We need to describe what causes the output to transition, in terms of when the input transitions.\u00a0 This\u00a0can be described as:<\/p>\n

inverter(in, out) = in+ <\/strong>\u21dd out- <\/strong>\u22c4 in- <\/strong>\u21dd out+<\/strong><\/p>\n

This is very similar to the buffer concept, but with some subtle differences.\u00a0 This concept implies that in+<\/strong> causes out-<\/strong>.\u00a0 This is composed with in- <\/strong>causing out+<\/strong>.\u00a0 Therefore, this concept suggest that when the input transitions one way, the output will eventually transition in the opposite direction, for example, when in+ <\/strong>occurs, out-<\/strong> will eventually occur after, providing in <\/strong>stays high<\/strong>.<\/p>\n

As with the previous post<\/a>, we need to produce an STG from the inverter concept, which we can simulate, verify and test.\u00a0\u00a0To do this, we pass this into the conversion\u00a0algorithm, which starts as follows:<\/p>\n

\"Buffer0\"<\/a><\/p>\n

As with the buffer, it starts off by placing cycles for each individual signal.\u00a0 This keeps the property of\u00a0consistency in the STG, as discussed in Concepts I<\/a><\/em>.<\/p>\n

\"inverter1\"<\/a><\/p>\n

Next, the first\u00a0causality of the inverter\u00a0concept is applied to these cycles.\u00a0 This is in+ \u21dd out-<\/strong>. This connects the place after\u00a0in+<\/strong>, labelled as\u00a0in_1<\/strong>, with the signal transition of out-<\/strong>, using a read-arc<\/em>. This is so that\u00a0for out- <\/strong>to occur, in <\/strong>must have already transitioned high<\/strong>, which is displayed by in_1<\/strong> possessing a token. The read-arc stops out-<\/strong> from consuming the token in in_1<\/strong> which would block in-<\/strong> from happening, but allows out-<\/strong>\u00a0to occur.<\/p>\n

\"inverterSTG2\"<\/a><\/p>\n

Finally, another read arc is used which represents the concept of in- <\/strong>\u21dd<\/strong> out+<\/strong>, connecting in_0<\/strong> place with the out+<\/strong> transition. This conversion of a concept to an STG is now complete, and this correctly represents the operation of an inverter.<\/p>\n

Note, as with the buffer STG,\u00a0that in the above STGs we assume that all signals are initialised to 0.\u00a0 In this case, it means that the output can initially transition high<\/strong> and will do eventually, due to the fact that in input is initially 0.<\/p>\n

In a later blog post we will see how to use concepts to specify initial states of all signals in a compositional manner.<\/p>\n

More reuse<\/span><\/strong><\/p>\n

We have now defined both an inverter and a buffer in these first two posts.\u00a0 So lets use these together to show some reuse, and how these can be used together.<\/p>\n

For this example, lets use a buffer and inverter loop.\u00a0 It doesn’t necessarily have any real-world applications as these logic gates, but it’s a perfect example to show how concepts can be composed, and produces some interesting results.<\/p>\n

\"bufferinverter\"<\/a><\/p>\n

The signals shown in this diagram are\u00a0simply used for viewing the outputs from the inverter and the\u00a0buffer, but can be used\u00a0as part of the concepts.<\/p>\n

This circuit can be produced from the following concept:<\/p>\n

bufferAndInverter = buffer(a,b)\u00a0\u22c4 inverter(b,a)<\/strong><\/p>\n

In this circuit, a<\/strong> is an input to the buffer, but the output from the inverter, and these are connected. \u00a0b<\/strong> is another signal connecting the output of the buffer<\/strong> to the input of the inverter<\/strong>.<\/p>\n

As with the doubleBuffer\u00a0<\/strong>example from the previous post,\u00a0we could have described this using signal-level concepts, which would be a longer description that that of the one above. Since we have defined both an inverter and a\u00a0buffer, we can simply reuse this definition in order to save time on describing concepts. The bufferAndInverter <\/strong>STG will be, assuming all signals are initially 0,\u00a0as follows:<\/p>\n

\"bufferAndInverterSTG\"<\/a><\/p>\n

By following pairs of arcs, it is possible to see which are a cause of the buffer, and which are a cause of the inverter.\u00a0 This STG can now be simulated, and does in fact act as expected from the circuit above.\u00a0 When a+ <\/strong>occurs, b+<\/strong> is enabled,\u00a0 and after it transitions, this will cause a-<\/strong> to be enabled.\u00a0 When a- <\/strong>has occurred, b-<\/strong> can then occur, after which a+<\/strong> is enabled, and this completes the circuit.<\/p>\n

This STG can be resynthesized, and the result is rather interesting:<\/p>\n

\"handshake1\"<\/a><\/p>\n

The resulting STG is in-fact the STG for a handshake protocol<\/strong><\/em>.\u00a0 This means that what we have defined above, bufferAndInverter<\/strong>, is actually a handshake<\/strong>, described using a buffer and an inverter.\u00a0 Therefore, let’s drop the current name, and re-define it using some parameters, so that any pair of signals can be handshaked.<\/p>\n

handshake(a,b)\u00a0= buffer(a,b)\u00a0\u22c4 inverter(b,a)<\/strong><\/p>\n

Handshakes are very useful for asynchronous systems, and having a concept defined for use at any time can make the design process much easier and quicker.<\/p>\n

Finally<\/strong><\/span><\/p>\n

In this post, we have discussed how to describe a second logic gate, an inverter. We have described this\u00a0in terms of concepts, and shown the conversion to produce an STG. We have also shown how a buffer and an inverter can be used\u00a0in conjunction with one-another\u00a0to produce a circuit, now that both have been pre-defined.<\/p>\n

The\u00a0next post, Concepts III:\u00a0Initial States <\/em><\/strong>will use buffers and inverters as examples of how initial states can be defined using concepts, or in the case that initial states are not defined, how the conversion algorithm will apply options for initial states, so an STG produced can still be used for simulation.<\/p>\n","protected":false},"excerpt":{"rendered":"

An inverter In the second post in the Concepts series we will discuss another simple logic gate, an inverter. An inverter takes an input signal, and outputs a signal in the\u00a0opposite, or inverted,\u00a0state as the input signal, the output is simply the opposite of the input. For example, if the input signal changes from 0 … Continue reading Concepts II: An inverter<\/span> →<\/span><\/a><\/p>\n","protected":false},"author":6010,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[3,2,7,6],"tags":[],"class_list":["post-58","post","type-post","status-publish","format-standard","hentry","category-asynchronous","category-concepts","category-inverter","category-logic-gate"],"_links":{"self":[{"href":"https:\/\/blogs.ncl.ac.uk\/jrbeaumont\/wp-json\/wp\/v2\/posts\/58","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.ncl.ac.uk\/jrbeaumont\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.ncl.ac.uk\/jrbeaumont\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.ncl.ac.uk\/jrbeaumont\/wp-json\/wp\/v2\/users\/6010"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.ncl.ac.uk\/jrbeaumont\/wp-json\/wp\/v2\/comments?post=58"}],"version-history":[{"count":17,"href":"https:\/\/blogs.ncl.ac.uk\/jrbeaumont\/wp-json\/wp\/v2\/posts\/58\/revisions"}],"predecessor-version":[{"id":91,"href":"https:\/\/blogs.ncl.ac.uk\/jrbeaumont\/wp-json\/wp\/v2\/posts\/58\/revisions\/91"}],"wp:attachment":[{"href":"https:\/\/blogs.ncl.ac.uk\/jrbeaumont\/wp-json\/wp\/v2\/media?parent=58"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.ncl.ac.uk\/jrbeaumont\/wp-json\/wp\/v2\/categories?post=58"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.ncl.ac.uk\/jrbeaumont\/wp-json\/wp\/v2\/tags?post=58"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}